This invention relates to a circuit for controlling input/output of data in a semiconductor device.
The configuration of a data input/output control circuit in a semiconductor device related to this invention is shown in FIG. 6. At an input/output terminal 15 to which data is inputted and from which data is outputted, an input/output circuit 14 is provided. This input/output circuit 14 includes N-channel transistors 16 and 17. Source of the N-channel transistor 16 is connected to power supply voltage VDD terminal, and drain of the N-channel transistor 16 is connected to the input/output terminal 15 together with drain of the N-channel transistor 17. Source of the N-channel transistor 17 is connected to ground voltage Vss terminal.
Respective gates of the N-channel transistors 16 and 17 are connected to the output side of an output circuit 13. The output circuit 13 includes two two-input NOR circuits 11 and 12, and their output terminals are respectively connected to the gates of transistors 16 and 17. To two input terminals of the NOR circuit 11, a signal line 102 through which an inverted signal /D obtained by inverting output data generated in an internal circuit (not shown) is transferred and a signal line 103 through which an output enable signal /OE is transferred are respectively connected. On the other hand, to two input terminals of the NOR circuit 12, a signal line 101 through which output data D is transferred and the signal line 103 are respectively connected.
This data input/output control circuit operates as follows. When output enable signal/OE of low level is inputted to the output circuit 13, two NOR circuits 11 and 12 operate as an inverter. When output data D is at low level (inverted signal /D is at high level), only N-channel transistor 17 is turned ON in the input/output circuit 14. As a result, a signal of low level is outputted from the input/output terminal 15. On the other hand, when output data is at high level (inverted signal /D is at low level), only N-channel transistor 16 is turned ON oppositely to the above. As a result, a signal of high level is outputted from the input/output terminal 15.
In the case where output enable signal /OE is at high level, NOR circuits 11 and 12 of the output circuit 13 both provide outputs of low level irrespective of data D (inverted signal /D). Thus, N-channel transistors 16 and 17 both maintain OFF state, placing the input/output terminal 15 in high impedance state. As a result, internal circuit (not shown) connected to the output circuit 13 and the input/output terminal 15 are electrically cut off. For this reason, it is possible to input data from the exterior through input/output terminal 15 to other internal circuits (not shown) connected to the input/output terminal 15.
However, there were the following problems in such data input/output control circuit. Since output control of data is carried out by using output enable signal /OE, at least one stage of gate (NOR circuits 11 and 12 in this example) is required between signal lines 101 and 102 for transferring data D and inverted signal /D and input/output circuit 14. This gate causes propagation delay of signal (data), so speed for outputting data to the exterior was lowered.
The configuration of another data input/output control circuit related to this invention is shown in FIG. 7. To signal lines 101 and 102 for transferring output data D and inverted signal /D, input terminals of clocked inverters 21 and 22 are respectively connected. When output enable signal /OE is at low level, these clocked inverters 21 and 22 operate as an inverter, while when it is at high level, their output sides are brought into high impedance state. Between output terminals of clocked inverters 21 and 22 and ground potential Vss terminal, drains of discharge N-channel transistors 23 and 24 are respectively connected. Respective conduction of these transistors 23 and 24 are controlled by output enable signal /OE. Further, gates of transistors 16 and 17 of the input/output circuit 14 are respectively connected to output terminals of clocked inverters 21 and 22 similarly to the circuit shown in FIG. 6.
In the circuit shown in FIG. 7, when output enable signal /OE is at low level, clocked inverters 21 and 22 operate as an inverter, and discharge transistors 23 and 24 are turned OFF. As a result, signals corresponding to the levels of output data D and inverted signal /D are outputted from the input/output terminal 15 to the exterior.
On the other hand, when the output enable signal /OE is at high level, clocked inverters 21 and 22 become inoperative, and transistors 23 and 24 become conductive. As a result, the output terminals of the clocked inverters 21 and 22 are discharged. As a result, signals of low level are inputted to gates of transistors 16 and 17 of the input/output circuit 14. Thus, these transistors are both turned OFF, so the input/output terminal 15 is placed in high impedance state. Thus, there results the state where input of data from the exterior to the input/output terminal 15 can be carried out.
Also in the data input/output control circuit shown in FIG. 7, at least one stage of gate is required between signal lines 101 and 102 and input/output circuit 14. For this reason, propagation delay of signal might take place similarly to the circuit shown in FIG. 6, resulting in lowered data output speed.
In addition, ON/OFF control of transistors 16 and 17 of the input/output circuit 14 is controlled by outputs from NOR circuits 11 and 12, or clocked inverters 21 and 22. At this time, noise may be produced by charge/discharge on the output terminals of NOR circuits 11 and 12, or clocked inverters 21 and 22. For this reason, there was the possibility that any erroneous operation might take place in the transistors 16 and 17.